The continuing trend in integrated circuits toward densification has led to reduced device dimensions and a decrease in size of components that make up the devices. However, in the fabrication of such devices as MOS transistors (metal-oxide semiconductors, or MIS or metal-insulating semiconductors), and with the trend toward higher performance and processing speeds, storage cells must maintain a minimum storage charge to ensure operation of memory cells. Several techniques have been developed to increase the storage capacity of a capacitor within a limited space. For example, surface area has been increased by forming the capacitor in a trench or as a stacked structure. The surface area of the capacitor has also been achieved by increasing the surface roughness of the lower electrode that forms the storage node.
Other techniques concentrate on the use of dielectric materials having high dielectric constants (k). Such materials include tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), and barium strontium titanate (BST). Such materials effectively possess dielectric constants greater than conventional dielectrics (e.g., silicon oxides and nitrides). Due to the high dielectric constant of Ta2O5 and other high K dielectrics, a thicker dielectric layer can be used in capacitor constructions to achieve the same capacitance level as thinner layers of other lower K dielectric materials, thus reducing cell leakage for the same effective oxide thickness (EOT).
Despite the advantages of high dielectric constant materials, difficulties have been encountered, however, in incorporating insulating inorganic metal oxide materials into semiconductor fabrications. Typically, the deposition of the dielectric layer and a subsequent anneal to densify the high K dielectric material to reduce leakage is conducted in the presence of an oxygen ambient. Undesirably, the oxygen ambient will react with the underlying lower capacitor plate, typically conductively doped polysilicon, to form a layer of silicon dioxide over the polysilicon that reduces the overall dielectric constant and thereby reduces the cell capacitance.
One solution that has been utilized is to provide an intervening oxidation barrier layer between the inorganic metal oxide dielectric layer and the underlying polysilicon electrode. Present methods include forming a silicon nitride layer over the polysilicon prior to formation of the Ta2O5 or other dielectric layer, by rapid thermal nitridization (RTN) of the polysilicon electrode. The nitride layer is used to reduce the oxidation of the lower polysilicon electrode during the deposition of the dielectric layer and subsequent oxidation and conditioning treatments. The subsequent treatment processes invariably oxidize the underlying polysilicon electrode to reduce the leakage of the dielectric-polysilicon stack. However, the overall capacitance is undesirably reduced due to the physical thickness of the subsequent oxynitride layer, which is typically up to 30 angstroms.
Thus, a need exists for a process for integrating high dielectric constant materials into semiconductor devices that avoids such problems.